A power supply may convert an input voltage having a first set of characteristics into an output voltage having another set of characteristics. For example, a power supply may convert 110 VAC from a power outlet into 9 VDC for powering or recharging the battery of a cell phone.
A DC-DC converter is a type of power supply that is widely used to supply DC power to electronic devices, such as computers, printers, and the like, and that is available in a variety of configurations for deriving a regulated DC output voltage from a DC source of input voltage. As a non-limiting example, a buck-mode or step-down DC-DC converter generates a regulated DC output voltage whose value is less than the value of the DC source voltage. A step-down DC-DC converter may include one or more power channels or phases, the outputs of which are combined at an output node for delivering a regulated stepped-down DC output voltage to a load. Each phase includes power switches and a current-flow path that includes a filter inductor. The power switches are, for example, controllably switched by a pulse-width-modulation (PWM) signal produced by a PWM modulator to switchably connect a DC source voltage to one end of the filter inductor, a second end of which is connected to the output node. Alternatively, the power switches may be controllably switched by constant-on-time pulses, constant-off-time pulses, or other types of pulses.
In addition to regulator implementations which have no mutual magnetic coupling among the filter inductors, there are regulator configurations which provide magnetic coupling among the filter inductors. These ‘coupled-inductor’ DC-DC converters have become increasingly attractive for supplying power to portable electronic devices, such as, but not limited to, notebook computers, and the like, which may operate in a discontinuous current mode (DCM) during low or relatively light load (e.g., quiescent or ‘sleep’ mode) conditions to reduce power loss and preserve battery life. For DCM operation, the upper and lower MOSFETs of at least one respective power switching stage of the converter are turned off for part of the switching period, preventing polarity reversal of the inductor current, so that the inductor current is zero during part of the switching period, i.e. it is discontinuous, rather than a continuous, thereby reducing current to the output to accommodate the relatively light current demand during such low-load conditions.
A non-limiting example of a conventional dual-phase, coupled-inductor buck-mode regulator or DC-DC converter, in which the filter inductors of the respective phases are mutually coupled with one another, is diagrammatically illustrated in FIG. 1. The dual-phase regulator of FIG. 1 comprises two phases that produce respective output currents iL1 and iL2, which flow from phase nodes 115 and 215 of respective phases 110 and 210 through respective filter inductors L1 and L2, which are mutually coupled with one another, such that a current magnetically induced in one phase by a switched or driven current flowing in the other stage flows in the same direction (from the phase node into the output node OUT) as the driven (inducing) current. These two currents are summed at an output node OUT to produce a composite or total output current Itotal. Output node OUT provides a regulated output voltage Vo for powering a device LOAD, such as the microprocessor of a notebook computer, through which a load current io flows.
In order to regulate the output voltage Vo, the voltage at the output node OUT is fed back to an error amplifier (EA) 310, which is operative to compare the monitored output voltage Vo with a reference voltage VID. The voltage-difference output Comp of the error amplifier 310 is supplied to a power-supply controller 315. For example, the controller 315 is operable to control the pulse widths of associated streams of pulse-width-modulation (PWM) waveforms that are applied by respective PWM generators within the controller to driver circuits, the outputs of which are coupled to the gates of, and control the on/off switching times of, the upper and lower switching devices (MOSFETs Q11/Q21 and MOSFETs Q12/Q22) of the phases 110 and 210. In an example application, the PWM waveforms are sequenced and timed such that the interval between rising edges (or in some implementations, falling edges) thereof is constant to substantially equalize the output currents iL1 and iL2 of the two power channels.
In addition to monitoring the output voltage Vo, error amplifier 310 may also monitor the sum of the phase currents iL1+iL2 via respective sense resistors Rsn1 and Rsn2, which are coupled between the phase nodes 115 and 215 and a first, non-inverting (+) input 321 of a (K gain) transconductance amplifier 320. Amplifier 320 has a second, inverting (−) input 322 coupled to the output node OUT, and a sense capacitor Csns connected across its inputs. The amplifier 320 allows the sum of the phase currents to be used to regulate the output resistance of the power supply according to a technique commonly known as droop regulation or load-line regulation. The voltage output Vdroop of the amplifier 320 is coupled to a first input 331 of a summer 330, a second input 332 of which is coupled to the output node OUT. The Vdroop voltage output (which is typically negative) of amplifier 320 is added to the output voltage Vo to provide a difference voltage Vdiff that is coupled to a first, inverting (−) input 311 of error amplifier 310. The second, non-inverting (+) input 312 of error amplifier 310 is coupled to receive the reference voltage VID. As described above, the output voltage Comp of error amplifier 310 is used by the controller 315 to control the pulse widths of the PWM waveforms that control the on/off switching of the upper and low MOSFETs of the phases 110 and 210.
Examples of these PWM waveforms are shown in FIG. 2 as including a first PWM waveform PH1, which is used to control the on/off switching of the upper MOSFET switch Q11 of the first phase 110, and a second PWM waveform PH2, which is used to control the on/off switching of the upper MOSFET switch Q21 of the second phase 210. For balanced-phase operation, the frequencies of the two PWM waveforms are substantially the same and the times of occurrence of the turn-on pulses Q11-ON of the first PWM waveform PH1 are midway between the times of occurrence of the turn-on pulses Q21-ON of the second PWM waveform PH2, and vice versa. That is, the turn-on pulses Q11-ON are spaced approximately 360°/N=180° from the turn-on pulses Q21-ON, where N=2=the number of power-supply phases. During the intervals that the pulses of the waveforms PH1 and PH2 are high, MOSFETs Q11 and Q21 are turned on thereby, so that increasing or ramping up segments iL1-1 and iL2-1 of respective currents iL1 and iL2 flow therethrough and, via phase nodes 115 and 215, through mutually coupled inductors L1 and L2 to the output node OUT.
As further shown in FIG. 2, when the turn-on pulse Q11-ON of the PWM waveform PH1 goes low, a PWM waveform VGS_Q12, which is used to control the on/off switching of the lower MOSFET switch Q12 of the first phase 110, transitions high for a prescribed period Q12-ON, corresponding to the pulse-width interval of PWM waveform VGS_Q12. With MOSFET switch Q12 turned on during this interval, the inductor current iL1 of the first channel gradually decreases or ramps down to zero from its peak value at the end of the duration of the turn-on pulse Q11-ON of PWM waveform PH1, as shown at iL1-2. The ramping down portion iL1-2 of the output current iL1 is supplied by a portion iS12-1 of a current iS12 that flows from ground through the source-drain path of the active MOSFET Q12 to phase node 115 and into the inductor L1.
In a like manner, when the turn-on pulse Q21-ON of the PWM waveform PH2 goes low, a PWM waveform VGS_Q22, which is used to control the on/off switching of the lower MOSFET switch Q22 of the second phase 210, transitions high for a prescribed period Q22-ON corresponding to the pulse-width interval of PWM waveform VGS_Q22. With MOSFET switch Q22 turned on during this interval, the inductor current iL2 of the second phase gradually ramps down to zero from its peak value at the end of the duration of the turn-on pulse Q21-ON of PWM waveform PH2, as shown at iL2-2. The ramping down portion iL2-2 of the output current iL2 is supplied by a portion iS22 of a current iS22 that flows from ground through the source-drain path of the active MOSFET Q22 to phase node 215 and into the inductor L2.
As pointed out above, because the inductor L1 of the phase 110 is mutually coupled with the inductor L2 of the phase 210, the current iL1 driven through inductor L1 as a result of the successive PWM-controlled turn on of the MOSFETs Q11 and Q12 magnetically induces a current in the inductor L2 of the second phase, shown in the current waveform iL2 of FIG. 2 as induced current iL2-3. Because the upper MOSFET Q21 of the second phase is off during this time (PH2 is low), and the polarity of its inherent body-diode is oriented so as to inherently block the flow of current therethrough from the input voltage supply rail Vin to phase node 215, no current is drawn through the upper MOSFET Q21 to supply the induced current iL2-3. MOSFET Q22 of the second phase is also off at this time, since its switching PWM waveform VGS_Q22 is low. However, the orientation of its body-diode allows the flow of a current iS22-2 from ground and through this body-diode as a body-diode current iD22 to phase node 215 and into inductor L2 as the induced current iL2-3.
In like manner, the current iL2 through inductor L2 that results from the successive PWM-controlled turn on of the MOSFETs Q21 and Q22 magnetically induces a current in the inductor L1 of the first phase, shown in the current waveform iL1 of FIG. 2 as induced current iL1-3. Because the upper MOSFET Q11 of the first phase is off and the polarity of its inherent body-diode is oriented so as to inherently block the flow of current therethrough from the input voltage supply rail Vin, no current is drawn through the upper MOSFET Q11 to provide the induced current iL1-3. However, even though the lower MOSFET Q12 of the first phase is off because its switching PWM waveform VGS_Q12 is low, the polarity orientation of its body-diode is such as to allow the flow of a current iS12-2 from ground and through the body-diode as a body-diode current iD12 to phase node 115 and into inductor L1 as the induced current iL1-3.
Unfortunately, because the two induced currents iL1-3 and iL2-3 are supplied by way of respective currents iD12 and iD22 through the body diodes of lower MOSFETs Q12 and Q22, these induced currents may cause significant conduction losses in these MOSFETs.